The invention generally relates to field effect transistors of the self-aligned metal gate type and, more particularly, to a method of fabricating same that avoids certain problems associated with high temperature processing steps.
Metal gates have been used to improve gate conductivity in high density self-aligned FET devices. Such use, however, can encounter significant difficulties, e.g., the penetration of the gate metal into the gate oxide (if the metal gate is present during high temperature fabrication steps) as well as otherwise damaging the gate oxide during the gate formation steps. These and other problems become intensified when the FET devices are reduced to the submicron range. Not only must the gate oxide be protected during the aforementioned processing steps, but that objective must be accomplished in a manner consistent with self-alignment techniques in order to achieve close dimensional control for high device density chip designs where there is a desire to avoid the need for advanced lithographic tools.
There are many examples in the prior art of the use of "sidewall" technology to define photolithography-free submicron-sized structures such as FET gates, for example, Japanese patent 42151 of March 1982, issued to Tokashi Itou and assigned to Fujitsu; Japanese patent 307739 of December 1988, issued to Michihiko Hasegawa and assigned to Fujitsu; Japanese patent 60131, issued February 1990 to Naomasa Oka and assigned to Matsushita Electric Works, Ltd.; U.S. Pat. No. 4,729,966 issued to Koshino et al on Mar. 8, 1988; U.S. Pat. No. 4,769,339 issued to Tetsuo Ishii on Sep. 6, 1988 (in the latter two patents, metal FET gates are left in place during high temperature source/drain annealing cycles); U.S. Pat. No. 4,312,680 issued to Sheng Hsu on Jan. 26, 1982; U.S. Pat. No. 4,358,340 issued to Horng-Sen Fu on Nov. 9, 1982; U.S. Pat. No. 4,559,693 issued to Kiyoho Kamei on Dec. 24, 1985.
More particularly, the above-cited U.S. Pat. Nos. 4,729,966 and 4,769,339 provide for sidewall metal gates which are used as masks during source and drain formation and remain in place during high temperature annealing for later use in the final structure. Some undesirable penetration of the metal into the gate oxide inevitably results.
The problem of gate metal penetration into gate oxide is avoided in U.S. Pat. No. 4,532,698, issued to Frank F. Fang, et al on Aug. 6, 1985. The metal gate is removed prior to annealing (after having served as a mask during source and drain ion implantation) and then is replaced by a second self-aligned metal gate. Yet another self-alignment technique, but still one in which a resist "dummy-gate" member is removed prior to source-drain anneal, is reported in the article p-Channel Germanium MOSFETS with High Channel Mobility, by Suzanne C. Martin et al, IEEE Electron Devices Letters, Vol. 10, No. 7, July 1989, p. 325. A metal gate is added after the annealing step is completed. Although the gate metal penetration problem alluded to above is avoided in the last two cited references, the gate oxide is left uncovered in both cases during the high temperature annealing step, exposing said oxide to latent contaminants present within the annealing furnace.